Title: Design of Scalable Reconfigurable Computing Systems: Frameworks, Architectures and Runtime Management

Duration: 08.22 – today

Research Area: Scalable Architectures

In a rapidly changing digital landscape with complex algorithms like machine learning, it is necessary to adopt new strategies that enhance flexibility and adaptability. Promising solutions include runtime scalability and adaptability for low-power and highly efficient hardware. By combining the runtime reconfiguration of FPGAs with the efficient communication of Networks-on-Chip (NoC), a highly scalable, high-performance, and energy-efficient computing architecture can be implemented.  However, designing efficient architectures and programming is becoming increasingly challenging. Therefore, developers require a comprehensive framework that offers efficient automation, good usability, reasonable abstraction, and seamless integration of different tools and libraries.

The project should provide an easy entry point for users and reduce the effort required to learn new concepts, programming languages, and tools.  The aim is to enable users to develop new applications without having to deal with the underlying details. Efficient algorithms are necessary to execute applications on heterogeneous architectures with maximum performance. The applications must be optimizable based on various objectives, such as performance or resource utilization. Moreover, the project aims to integrate all the necessary steps to make FPGAs more accessible to users who may not possess extensive hardware knowledge.

Aims

We aim to investigate the various stages involved in developing a runtime scalable and reconfigurable FPGA-based system for future highly adaptive applications (such as computer vision and machine learning), focusing on:

• Frameworks: developing automated workflows, handling various design phases: auto-generating architectures, auto-transforming and auto-implementing of runtime-adaptive architectures.
• Usability, modularity and integration: utilizing standards like OpenVX. Implementing libraries and improving software-oriented approaches to abstract hardware aspects.
• Architectures: developing scalable architectures, adapting performance at runtime for optimal resource usage, achieving enhanced results in dynamic or unpredictable conditions.

Problem

The field of highly adaptive applications, such as computer vision (CV) and machine learning (ML), is growing in complexity and diversity. Field-programmable gate arrays (FPGAs) have proven their ability to meet the increasing demands for performance and energy efficiency. However, their programmability remains a major challenge for software developers. Users frequently encounter different or new languages, architectures, and tools, and do not have in-depth knowledge of the underlying FPGA hardware. Furthermore, there is often a lack of linkages between vendors, defined standards or model-based modularization to bring it all together.

Practical example

We have developed a framework that generates a runtime-adaptive vision architecture from OpenVX applications that is both high-performance and flexible. This architecture is designed for applications with high data rates and low synchronization overhead. In addition, we have implemented a scalable and runtime-adaptive architecture that dynamically adjusts the number of accelerators at runtime according to the current needs of the application. Please refer to our publications for further information and preliminary results.

Technology

The technology we use is divided into three areas. Firstly, for the framework used for auto-generating architectures, we use model-based approaches and divide the phases into frontend, middleware, and backend. Secondly, to make the architecture adaptive, we use AMD Xilinx’s Dynamic Function eXchange (DFX) technology. The IPs used as accelerators are based on HiFlipVX. Scalability is achieved through the use of a network-on-chip communication subsystem. Thirdly, for workflow and back-end automation, we use scripting language-based approaches. We use various AMD Xilinx FPGAs to test and validate our work.

Outlook

The research should support the usage of FPGAs in the field of computer vision with a focus on convolutional neural networks. It should help software developers the usage of FPGAs and their systems. It should also help the creation of hardware architectures with only limited knowledge of hardware. In future we would like to investigate more into different standards, integration into other frameworks and looking at other application areas that consider the usage of neural network-based architectures.

Publications

• Lester Kalms, Tim Häring, Diana Göhringer, “DECISION: Distributing OpenVX Applications on CPUs, GPUs and FPGAs using OpenCL”, 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
• Najdet Charaf, Julian Haase, Adrian Kulisch, Christian von Elm, Nico Volkens, Diana Göhringer,    “RTASS: a RunTime Adaptable and Scalable System for Network-on-Chip-based Architectures” 2023 IEEE Euromicro Conference Series on Digital System Design (DSD)
• Lester Kalms, Matthias Nickel, Diana Göhringer, “ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures”, 2023 Springer International Symposium on Applied Reconfigurable Computing (ARC)

Team

Lead

Prof. Dr. Diana Göhringer

Team Members

• Najdet Charaf
• Lester Kalms